The present invention relates to the field of electronic communications systems and methods. More particularly, the present invention relates to a system and method to optimize read performance while accepting write data in a peripheral communications interconnect (PCI) bus architecture.
Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems include processors that have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results include a variety of components that communicate with each other via a communication bus such as a peripheral component interconnect (PCI) bus. The order and speed at which the components communicate with one another over the bus without having to repeat read and write commands has a substantial impact on the performance of the computer system.
Typically a bus consists of several lines of electrically conductive material. The bus permits electrical signals representing data and control instructions to be readily transmitted between different components (agents) coupled to the bus. The industry standard PCI specification dictates that when a PCI agent requires the use of a PCI bus to transmit or receive data, the PCI agent requests PCI bus xe2x80x9cownershipxe2x80x9d from a PCI arbiter. The PCI agent requesting ownership is referred to as a PCI initiator agent, or master device. Typically, each of the PCI agents may independently act as a PCI initiator agent and request PCI bus ownership. The PCI agent the PCI initiator agent attempting to communicate with is referred to as a PCI target agent or slave device. After the PCI initiator agent has been granted PCI bus ownership that the PCI initiator agent attempts to access the PCI target agent and initiate a PCI transaction (e.g., data transfer).
The PCI initiator agent begins the PCI transaction by identifying or addressing the PCI target agent during the address phase of the PCI transaction. Once the PCI target agent senses it is being addressed, continuation of a PCI transaction is dependent on the PCI target agent. If the PCI target agent indicates it is ready the PCI transaction continues. However, if the PCI target agent is not ready for the PCI transaction to continue, it signals the PCI initiator agent to retry. For example, if an initiator issues a read command to a target the target usually registers the read as a delayed or pending read request. In a pending read request situation the target issues a retry to the initiator immediately to avoid tying up the PCI bus while the target locates the information and downloads it to a read buffer. By signaling a retry, the PCI target agent is instructing the PCI initiator agent to stop the current PCI transaction and try to complete it later. However, while the target is servicing the read request another initiator (or the same initiator) could request the target with postable write data.
Postable write data to the same address or location associated with a read command creates a potential for deadlock and coherency problems on the PCI bus that is addressed by PCI 2.2 specification. If a target decides to accept the write data, according to PCI 2.2 specification it should invalidate or discard the pending delayed read request in order to avoid a data coherency problem. More information details regarding deadlocks and coherency issues on Read Transactions with intermediate write transactions are addressed in the Appendix E of PCI Local Bus 2.2 specification under the subsection titled xe2x80x9cOrdering of Transactionsxe2x80x9d. While discarding a delayed read request addresses some of the coherency issues it severely degrades read performance, especially in situations where the condition repeats itself quickly.
Given the general proposition that the faster information and signals are communicated, the better the performance of a computer system, most PCI initiator agents are designed to complete their access in the minimum time possible. Accordingly, when the PCI initiator agent receives a retry from the PCI target agent, the PCI initiator agent deasserts the request for the minimum time allowed by PCI standards (i.e., two PCI clocks) and then retries the access. However, the PCI initiator agent""s quickly repeated retry attempts often occur before the PCI target agent has had sufficient time to clear the condition that caused it to issue the retry in the first place.
Repeating pending read quest requests significantly impacts a system""s performance capabilities. For example, much of a computer systems functionality and utility is realized through the use of components referred as peripheral devices. Frequently the speed at which peripheral devices interact with the rest of the computer system is critical. For many peripheral devices, such as graphics adapters, full motion video adapters, small computer system interface (SCSI) host bust adapters, and the like, it is imperative that large block data transfers be accomplished expeditiously. For example, the speed at which a graphics adapter can read information from a memory and communicate it to a monitor is a major factor in the computer systems usefulness as an entertainment device. However, if a network card is attempting to perform a direct memory access write to the memory at the same time according to PCI 2.2 specification the pending graphics read is discarded. In a graphics system repeated pending read discards often result in discontinuous streams that appears as glitches on a monitor. Hence the rate at which data can be transferred among various peripheral devices without having to repeat read and write commands often determines whether the computer systems is suited for a particular purpose.
What is required is a system and method that minimizes discarding of a pending read transaction due to an arrival of a write request while maintaining appropriate transaction ordering. Appropriate transaction ordering should reduce the potential of deadlock situations or coherency problems when a pending read address is being process and a write request is received. The system and method should prevent a write transaction from writing to an address that is associated with a pending read transaction that is being processed.
The present invention is a system and method that minimizes discarding of a pending read transaction due to an arrival of a write request while maintaining appropriate transaction ordering. The transaction ordering of the present invention reduces the potential of deadlock situations and coherencey problems when a pending read address is being processed and a write request is received. The system and method of the present invention prevents a write transaction from writing to an address that is associated with a pending read transaction that is being processed. The read/write optimizing system and method of the present invention optimizes read performance while accepting write data in a PCI bus architecture. The present invention facilitates the continued processing of a pending read under appropriate conditions by inhibiting a write transaction request directed to the target.
In one embodiment of the read/write optimizing system and method of the present invention, a write transaction is inhibited by tracking or storing an inhibited write transaction target address if a pending read transaction address is not within a range of an inhibited write transaction address. For example, a target address associated with an inhibited write transaction is temporarily latched in a write address register until a pending read transaction is completed or terminated. During the same time frame the inhibited write transaction is also partially processed (e.g., write data is loaded in a target write buffer) if a target is prepared and a pending read transaction address does not come within a range of an inhibited write transaction address as the pending read and inhibited write transactions are processed.